module div_us#(
parameter DVI_CNT = 50
)
(
	input			SYS_RST_N,
	input			SYS_CLK,
	output	reg		US_P
);

//===========================
function integer clogb2 (input  integer depth);
begin
    for(clogb2 = 0; depth > 0; clogb2 = clogb2 + 1)
        depth = depth >> 1;
end
endfunction
//==========================
reg     [clogb2(DVI_CNT) -1 :0 ] us_r;

always @ (posedge SYS_CLK)
	if(~SYS_RST_N)
	begin
		us_r <= 0;
		US_P <= 1'b0;
	end
	else 
	begin
		if(us_r == DVI_CNT)
		begin
			us_r <= 0;
			US_P <= 1'b1;
		end
		else
		begin
			us_r <= us_r + 1;
			US_P <= 1'b0;
		end
				
	end	
endmodule
